High Speed Semiconductor Devices

ABSTRACT

Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device according to the present disclosure includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a gate cut feature adjacent the gate structure, a source/drain contact isolation feature adjacent the source/drain contact, a spacer extending along a sidewall of the gate cut feature and a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact isolation feature and a sidewall of the source/drain contact; and an air gap sandwiched between the spacer and the liner. The gate cut feature and the source/drain contact isolation feature are separated by the spacer, the air gap and the liner.

PRIORITY DATA

This application is a divisional application of U.S. Pat. ApplicationNo. 16/406,154, filed May 8, 2019, which claims the benefit of U.S.Provisional Application No. 62/769,922, filed Nov. 20, 2018, each ofwhich is incorporated herein by reference in its entirety.

BACKGROUND

The electronics industry has experienced an ever-increasing demand forsmaller and faster electronic devices which are simultaneously able tosupport a greater number of increasingly complex and sophisticatedfunctions. Accordingly, there is a continuing trend in the semiconductorindustry to manufacture low-cost, high-performance, and low-powerintegrated circuits (ICs). Thus far these goals have been achieved inlarge part by scaling down semiconductor IC dimensions (e.g., minimumfeature size) and thereby improving production efficiency and loweringassociated costs. However, such scaling has also introduced increasedcomplexity to the semiconductor manufacturing process. Thus, therealization of continued advances in semiconductor ICs and devices callsfor similar advances in semiconductor manufacturing processes andtechnology.

Recently, multi-gate devices have been introduced in an effort toimprove gate control by increasing gate-channel coupling, reduceOFF-state current, and reduce short-channel effects (SCEs). One suchmulti-gate device that has been introduced is the fin field-effecttransistor (FinFET). The FinFET gets its name from the fin-likestructure which extends from a substrate on which it is formed, andwhich is used to form the FET channel. FinFETs are compatible withconventional complementary metal-oxide-semiconductor (CMOS) processesand their three-dimensional structure allows them to be aggressivelyscaled while maintaining gate control and mitigating SCEs. However, evenwith the introduction of FinFETs, aggressive scaling down of ICdimensions has resulted in increased parasitic capacitance (e.g.,between a FinFET gate and source/drain regions or source/draincontacts). As a result of such increased parasitic capacitance, deviceperformance is degraded. Thus, existing techniques have not provedentirely satisfactory in all respects.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is perspective view of an embodiment of a FinFET device accordingto one or more aspects of the present disclosure;

FIG. 2 is a flow chart of a method of fabricating a semiconductor deviceincluding an air gap sidewall spacer, in accordance with someembodiments;

FIGS. 3-8 provide cross-sectional views along a plane substantiallyparallel to a plane defined by section A-A′ of FIG. 1 , of an exemplarydevice fabricated according to one or more steps of the method of FIG. 2; and

FIG. 9 provides a cross-sectional view along a plane substantiallyparallel to a plane defined by section A-A′ of FIG. 1 of anotherexemplary device fabricated according to one or more steps of the methodof FIG. 2 .

FIG. 10 provides a cross-sectional view along a plane substantiallyparallel to a plane defined by section A-A′ of FIG. 1 of anotherexemplary device fabricated according to one or more steps of the methodof FIG. 2 .

FIG. 11 provides a cross-sectional view along a plane substantiallyparallel to a plane defined by section A-A′ of FIG. 1 of anotherexemplary device fabricated according to one or more steps of the methodof FIG. 2 .

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature’s relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

It is also noted that the present disclosure presents embodiments in theform of multi-gate transistors or fin-type multi-gate transistorsreferred to herein as FinFET devices. Such a device may include a P-typemetal-oxide-semiconductor FinFET device or an N-typemetal-oxide-semiconductor FinFET device. The FinFET device may be adual-gate device, tri-gate device, bulk device, silicon-on-insulator(SOI) device, and/or other configuration. One of ordinary skill mayrecognize other embodiments of semiconductor devices that may benefitfrom aspects of the present disclosure. For example, some embodiments asdescribed herein may also be applied to gate-all-around (GAA) devices,Omega-gate (Ω-gate) devices, or Pi-gate (Π-gate) devices.

This application relates to semiconductor device structures and methodsof forming the same, particularly high-speed semiconductor devicestructures and methods. A semiconductor device structure of the presentdisclosure includes air gaps on both sides of a gate structure, bothsides of a source/drain contact, both sides of an gate contact viaoverlying the gate structure, and both sides of a source/drain contactvia overlying the source/drain contact to reduce parasitic capacitanceand increase speed of the semiconductor device. A semiconductorstructure according embodiments of the present disclosure may include afin extending from a surface of a substrate. The fin may include achannel region and source/drain regions adjacent the channel region. Thesemiconductor structure may include a gate structure extending over thechannel region and a source/drain contact over the source/drain region.The semiconductor structure may also include a gate contact via over andelectrically coupled to the gate structure and a source/drain contactvia over and electrically coupled to the source/drain contact. The gatestructure and the gate contact via are laterally sandwiched betweenspacers extending along sidewalls of the gate structure. Thesource/drain contact and the source/drain contact via are laterallysandwiched between liners extending along sidewalls of the source/draincontact. A spacer and an adjacent liner is separated by an air gapextending vertically from a bottom of the gate structure to near a topsurface of the gate contact via or a top surface of the source/draincontact via. These vertically extending air gaps serve as extremelylow-k spacers that reduce parasitic capacitance formed among conductivefeatures (such as the gate structures, source/drain contacts, gatecontact vias and source/drain contact vias) and increase the speed ofthe semiconductor device.

Illustrated in FIG. 1 is a FinFET device 100. The FinFET device 100includes one or more fin-based, multi-gate field-effect transistors(FETs). While the embodiments of the present disclosure are describedusing the FinFET device 100 in FIG. 1 as an example, the presentdisclosure is not so limited and may be applicable to other type of FETsthat include semiconductor features other than the fin-elements shown infigures of the present disclosure. The FinFET device 100 includes asubstrate 102, at least one fin-element 104 extending from the substrate102, isolation regions 106, and a gate structure 120 disposed on andaround the fin-element 104. The substrate 102 may be a semiconductorsubstrate such as a silicon substrate. The substrate may include variouslayers, including conductive or insulating layers formed on asemiconductor substrate. The substrate 102 may include various dopingconfigurations depending on design requirements as is known in the art.The substrate 102 may also include other semiconductors such asgermanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond.Alternatively, the substrate 102 may include a compound semiconductorand/or an alloy semiconductor. Further, in some embodiments, thesubstrate 102 may include an epitaxial layer (epi-layer), the substrate102 may be strained for performance enhancement, the substrate 102 mayinclude an SOI structure, and/or the substrate 102 may have othersuitable enhancement features.

The fin-element 104 (or fin 104), like the substrate 102, may comprisesilicon or another elementary semiconductor, such as germanium; acompound semiconductor including silicon carbide, gallium arsenide,gallium phosphide, indium phosphide, indium arsenide, and/or indiumantimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs,AlGaAs, InGaAs, GaInP, and/or GaInAsP; or combinations thereof. The fins104 may be fabricated using suitable processes includingphotolithography and etch processes. The photolithography process mayinclude forming a photoresist layer (resist) overlying the substrate 102(e.g., on a silicon layer), exposing the resist to a pattern, performingpost-exposure bake processes, and developing the resist to form amasking element including the resist. In some embodiments, patterningthe resist to form the masking element may be performed using anelectron beam (e-beam) lithography process. The masking element may thenbe used to protect regions of the substrate 102 while an etch processforms recesses into the substrate 102, thereby leaving an extending fin104. The recesses may be etched using a dry etch (e.g., chemical oxideremoval), a wet etch, and/or other suitable processes. Numerous otherembodiments of methods to form the fins 104 on the substrate 102 mayalso be used.

Each of the plurality of fins 104 also include a source/drain region 105where the source/drain region 105 is formed in, on, adjacent and/orsurrounding the fin 104. It is noted that in a FET, such as the FinFETdevice 100, a channel region is sandwiched between a source region and adrain region. For ease of reference and description, the source regionand the drain region on different sides of a channel region is referredgenerally as the source/drain region, represented by the source/drainregion 105 shown in FIG. 1 . The source/drain regions 105 may beepitaxially grown over the fins 104. A channel region of a transistor isdisposed within the fin 104, underlying the gate structure 120, along aplane substantially parallel to a plane defined by section A-A′ of FIG.1 . In some examples, the channel region of the fin includes ahigh-mobility material such as germanium, as well as any of the compoundsemiconductors or alloy semiconductors discussed above and/orcombinations thereof. High-mobility materials include those materialswith an electron mobility greater than silicon. For example, higher thanSi which has an intrinsic electron mobility at room temperature (300 K)of around 1350 cm²/V-s and a hole mobility of around 480 cm²/V-s, insome instances.

The isolation regions 106 may be shallow trench isolation (STI)features. Alternatively, a field oxide, a LOCOS feature, and/or othersuitable isolation features may be implemented on and/or within thesubstrate 102. The isolation regions 106 may be composed of siliconoxide, silicon nitride, silicon oxynitride, fluorine-doped silicateglass (FSG), a low-k dielectric, combinations thereof, and/or othersuitable material known in the art. In an embodiment, the isolationstructures are STI features and are formed by etching trenches in thesubstrate 102. The trenches may then be filled with isolating material,followed by a chemical mechanical polishing (CMP) process. However,other embodiments are possible. In some embodiments, the isolationregions 106 may include a multi-layer structure.

The gate structure 120 includes a gate stack including a gate dielectriclayer 108, and a metal layer 122 formed over the gate dielectric layer108. In some embodiments, the gate dielectric layer 108 may include aninterfacial layer formed over the channel region of the fin 104 and ahigh-K dielectric layer over the interfacial layer. The interfaciallayer of the gate dielectric layer 108 may include a dielectric materialsuch as silicon oxide layer (SiO₂) or silicon oxynitride (SiON). Thehigh-K dielectric layer of the gate dielectric layer 108 may includeHfO₂, TiO₂, HfZrO, Ta₂O₃, HfSiO₄, ZrO₂, ZrSiO₂, combinations thereof, orother suitable materials. In still other embodiments, the gatedielectric layer 108 may include silicon dioxide or another suitabledielectric. The gate dielectric layer 108 may be formed by chemicaloxidation, thermal oxidation, atomic layer deposition (ALD), physicalvapor deposition (PVD), chemical vapor deposition (CVD), and/or othersuitable methods. The metal layer 122 may include a conductive layersuch as W, TiN, TaN, WN, Re, Ir, Ru, Mo, Al, Cu, Co, Ni, combinationsthereof, and/or other suitable compositions. In some embodiments, themetal layer 122 may include a first group of metal materials for N-typeFinFETs and a second group of metal materials for P-type FinFETs. Thus,the FinFET device 100 may include a dual work-function metal gateconfiguration. For example, the first metal material (e.g., for N-typedevices) may include metals having a work function substantially alignedwith a work function of the substrate conduction band, or at leastsubstantially aligned with a work function of the conduction band of thechannel region of the fin 104. Similarly, for example, the second metalmaterial (e.g., for P-type devices) may include metals having a workfunction substantially aligned with a work function of the substratevalence band, or at least substantially aligned with a work function ofthe valence band of the channel region of the fin 104. Thus, the metallayer 122 may provide a gate electrode for the FinFET device 100,including both N-type and P-type FinFET devices 100. In someembodiments, the metal layer 122 may alternately include a polysiliconlayer. The metal layer 122 may be formed using PVD, CVD, electron beam(e-beam) evaporation, and/or other suitable process.

In some embodiments, a replacement gate process (or gate replacementprocess) may be used to form the gate structure 120. In a replacementgate process, a sacrificial gate structure or a dummy gate is firstformed of a semiconductor material, such as polysilicon, over thechannel region to serve as a placeholder for the final gate structure isto be formed. After features around the dummy gate are fabricated, thedummy gate will be removed and replaced with the final gate structure.When the replacement gate process is used, multiple spacers (or spacerlayers) may be formed over the dummy gate. Spacers formed on the topsurface of the dummy gate structure may be removed at a later stage toallow access to and removal of the dummy gate structure. In someembodiments represented in FIG. 1 , two spacers- the first spacer 110and the second spacer (not shown, removed in FIG. 1 ) are formed overthe dummy gate. A liner may be formed over the sidewall of the secondspacer. After the dummy gate is removed and replaced by the gatestructure 120, these two spacers and the liner may remain along thesidewalls of the gate structure 120. The spacers and the liner mayinclude a dielectric material such as silicon oxide, silicon nitride,silicon carbide, silicon oxynitride, silicon oxy-carbide, siliconcarbide nitride, silicon oxy-carbide nitride, aluminum oxide, aluminumoxynitride, aluminum nitride, zirconium oxide, zirconium aluminumoxynitride, aluminum nitride, amorphous silicon, or combination thereof.In some embodiments, the second spacer is removed, leaving an air gap112 between the first spacer 110 and the liner 114. The air gap 112 inFIG. 1 is plugged from the top by the first sealing layer 140.

In some embodiments, to prevent the metal layer 122 from being etched oroxidized in later processes, a gate cap layer 124 may be formed over themetal layer 122. The gate cap layer 124 may be formed of tungsten,cobalt, nickel, ruthenium, titanium, titanium nitride, tantalum,tantalum nitride. In some implementations, a gate dielectric cap may beformed over the gate cap layer 124. In FIG. 1 , the gate dielectric caphas been removed after the formation of the gate contact via 126 throughthe gate dielectric cap and replaced with a first sealing layer 140. Inthe embodiments represented in FIG. 1 , the gate contact via 126 extendsvertically through the first sealing layer 140 and is electricallycoupled to metal layer 122 via the cap layer 124. The metal layer 122may be referred to as the gate structure.

The FinFET device 100 may include a source/drain contact 132electrically coupled to the source/drain region 105. To electricallycouple the source/drain contact 132 to the source/drain region 105, thesource/drain region 105 may be recessed and a silicide layer may beformed between the recessed source/drain region 105 and the source/draincontact 132. In some implementations, an etch stop layer may be formedover the source/drain region 105 before the source/drain region 105 isrecessed. Then a silicide precursor, such as nickel, cobalt andtitanium, is deposited over the recessed source/drain region 105. Asilicide feature, such as nickel silicide, cobalt silicide or titaniumsilicide may be formed over the recessed source/drain region 105 afterannealing. The silicide feature may reduce the contact resistancebetween the source/drain region 105 and the source/drain contact 132.Similar to the metal layer 122, a source/drain cap layer 134 may beformed over the source/drain contact 132. The source/drain cap layer 134may be formed of tungsten, cobalt, nickel, ruthenium, titanium, titaniumnitride, tantalum, tantalum nitride. Thereafter, a source/drain contactvia 136 may be formed over the source/drain cap layer 134 for routingthrough a metal line in a metal layer or an interconnect structure.Although not shown in FIG. 1 , the silicide feature, the source/draincontact 132, the source/drain cap layer 134, and the source/draincontact via 136 may be formed over the source/drain region 105 while thesource/drain region 105 is generally covered by a dielectric layer. InFIG. 1 , the dielectric layer is not shown because it has been removedalong with the second spacer layer and replaced with the first sealinglayer 140.

As noted above, aggressive scaling down of IC dimensions has resulted inincreased parasitic capacitance (e.g., between a FinFET gate andsource/drain regions or source/drain contacts, or between), thusdegrading device performance. In particular, the parasitic capacitancecontribution of sidewall spacers has become a greater portion of thetotal parasitic capacitance of a FinFET device. To address this issue,air gaps or air gap sidewall spacers have been introduced, for example,as a replacement to one of more of the dielectric materials used inconventional sidewall spacers (e.g., such as formed on sidewalls of thegate structure 120). In various embodiments, air gaps provide a lowerdielectric constant than the dielectric materials used in conventionalsidewall spacers. Thus, devices that employ air gaps generally havereduced parasitic capacitance and improved performance. However, suchair gaps end around a top surface of the gate structure and are notsimilarly introduced between gate contact vias and source/drain contactvias. As a result, gate contact vias and source/drain contact vias areeither made slim or are intentionally spaced apart from one another toensure sufficient dielectric material between them. By doing that,current flow through contact vias may be restricted and freedom forrouting design may be limited.

Embodiments of the present disclosure offer advantages over the existingart, though it is understood that other embodiments may offer differentadvantages, not all advantages are necessarily discussed herein, and noparticular advantage is required for all embodiments. For example,embodiments discussed herein include structures and methods forproviding an air gap (e.g., protected by multiple layers of sealmaterials) that provides a reduced spacer dielectric constant andenhanced device performance. In particular, embodiments disclosed hereinprovide for the formation of air gaps that not only separate gatestructures from source/drain contacts, but also separate gate contactvias from source/drain contact vias, along a direction parallel to a topsurface (or primary surface) of the substrate.

Referring now to FIG. 2 , illustrated is a method 200 of fabricating asemiconductor device 300 (e.g., such as a FinFET device, also referredto as device 300) including an air gap, in accordance with one or moreembodiments. In some embodiments, the method 200 may be used tofabricate the FinFET device 100, described above with reference to FIG.1 . Thus, one or more aspects discussed above with reference to theFinFET device 100 may also apply to the method 200. Additionally, FIGS.3-8 provide cross-sectional views, along a plane substantially parallelto a plane defined by section A-A′ of FIG. 1 , of an exemplary device300 fabricated according to one or more steps of the method 200 of FIG.2 . It is noted, while FIG. 1 and FIG. 3 may include different devicefeatures and aspects, they may nevertheless be snapshots of a singlesemiconductor device.

It is understood that parts of the method 200 and/or the semiconductordevice 300 may be fabricated by a well-known CMOS technology processflow, and thus some processes are only briefly described herein. Inaddition, as described above, the device 300 may share aspects of thedevice 100, thus some aspects and/or processes of the device 300 areonly discussed briefly for purposes of clarity in understanding.Further, the semiconductor device 300 may include various other devicesand features, such as additional transistors, bipolar junctiontransistors, resistors, capacitors, diodes, fuses, etc., but issimplified for a better understanding of the inventive concepts of thepresent disclosure. Further, in some embodiments, the semiconductordevice 300 includes a plurality of semiconductor devices (e.g.,transistors), which may be interconnected.

In various embodiments, the device 300 may be an intermediate devicefabricated during processing of an integrated circuit, or portionthereof, that may comprise static random access memory (SRAM) and/orother logic circuits, passive components such as resistors, capacitors,and inductors, and active components such as P-channel field-effecttransistors (PFETs), N-channel FETs (NFETs), metal-oxide-semiconductorfield-effect transistors (MOSFETs), high voltage transistors, highfrequency transistors, other memory cells, and/or combinations thereof.

Referring now to the method 200, the method 200 begins at block 202where a FinFET device 300 is provided. While being fabricated, theFinFET device 300 may be referred to as a workpiece from time to timeherein. In that sense, a workpiece having the FinFET device 300 thereonis received at block 202. The FinFET device 300 may include a gatestructure 320, a source/drain contact 332, and at least two spacersformed along a sidewall of the gate structure 320. Referring to FIG. 3 ,illustrated therein is a FinFET device 300 including a fin 302 thatextends from a substrate. The fin 302 includes channel regions 304 andsource/drain region 305 adjacent to the channel region 304. The FinFETdevice 300 also includes the gate structure 320 that includes a gatedielectric layer 308, and a metal layer 322 over the gate dielectriclayer 308. In some embodiments, the substrate, the fin 302, the gatedielectric layer 308, and the metal layer 322 may be substantiallysimilar to the substrate 102, the fin-elements 104, the gate dielectriclayer 108, and the metal layer 122 discussed above with reference toFIG. 1 . In some examples, the metal layer 322 has a height of around30-40 nm. In some implementations, the FinFET device 300 may alsoinclude a gate cap layer 324 disposed over the metal layer 322 and afirst dielectric layer 316 over the gate cap layer 324. In someinstances, the first dielectric layer 316 may be referred to as a firstself-aligned contact (SAC) dielectric or SAC1 layer. In the embodimentsrepresented in FIG. 3 , the FinFET device 300 includes two spacers - thefirst spacer 310 and the second spacer 312. In some embodiments, each ofthe first spacer 310 and the second spacer 312 may be formed to a widthbetween about 5 nm and about 10 nm. As described above, because spacersare formed by depositing spacer material over a dummy gate, followed byremoval of the dummy gate, a gate spacer would be illustrated on bothsides of the gate structure 320. In some embodiments, the metal layer322 may be formed of a conductive layer such as W, TiN, TaN, WN, Re, Ir,Ru, Mo, Al, Cu, Co, Ni, combinations thereof, and/or other suitablecompositions.

In some embodiments, the source/drain region 305 of the device 300includes epitaxial source/drain features which may be formed by one ormore epitaxial processes. In some cases, the epitaxial source/drainfeatures may be formed in, on, and/or surrounding the fin 302 in thesource/drain region 305. It is noted that for ease of illustration, thefin 302 is illustrated in FIGS. 3-8 as being flat along the Y direction.In some instance, the profile of the fin 302 along line A-A′ may not beflat due to various reasons, including, for example, the presence of thesource/drain features and recess of the source/drain features. A liner314 may be formed over the source/drain region 305 and sidewalls of thesecond spacers 312. In various examples, after liner material over topsurface of the epitaxial source/drain features are removed, a silicidelayer may be formed over the epitaxial source/drain features to reducecontact resistance. In some embodiments, the silicide layer may includeCo silicide, Ni silicide, or Ti silicide. Further, in some embodiments,a source/drain contact 332 may be formed over the silicide layer toprovide electrical contact to the epitaxial source/drain features. In atleast some examples, the source/drain contact 332 includes a Co layer,although other suitable metals may be used without departing from thescope of the present disclosure. In some embodiments represented in FIG.3 , the gate structure 320 is sandwiched between two first spacers 310,which are further sandwiched between two second spacers 312 from bothsides of the gate structure 320 along the Y direction. The source/draincontact 332 is sandwiched between two liners 314. In these embodiments,the second spacer 312 is interposed between the first spacer 310 and theliner 314. As illustrated in FIG. 3 , a source/drain cap layer 334 maybe formed over the source/drain contact 332 and a second dielectriclayer 318 (or a second SAC dielectric layer 318 or SAC2) may be formedover the source/drain cap layer 334. The workpiece for the FinFET device300 in FIG. 3 is planarized using chemical mechanical polishing (CMP) orother suitable grinding techniques.

In some embodiments, the gate cap layer 324 and the source/drain caplayer 334 may be formed of the same material or different materials. Forexample, the gate cap layer 324 and the source/drain cap layer 334 maybe formed of W, Co, Ni, Ru, Ti, Ta, TiN, TaN, combinations thereof,and/or other suitable compositions. In some instances, the gate caplayer 324 and the source/drain cap layer 334 may be formed at atemperature between about 300° C. and about 400° C., under a pressurebetween about 1 Torr and about 10 Torr. In some implementations, thegate cap layer 324 and the source/drain cap layer 334 may be formed to athickness between about 3 nm and about 30 nm.

In some embodiments, the first spacer 310, the second spacer 312, theliner 314, the first SAC dielectric layer 316, the second SAC dielectriclayer 318 may include a dielectric material such as silicon oxide,silicon nitride, silicon carbide, silicon oxynitride, siliconoxy-carbide, silicon carbide nitride, silicon oxy-carbide nitride,aluminum oxide, aluminum oxynitride, aluminum nitride, zirconium oxide,zirconium aluminum oxynitride, aluminum nitride, amorphous silicon, or acombination thereof. They can be formed using CVD, ALD, plasma-enhancedCVD (PECVD), plasma-enhanced-ALD (PEALD), or other suitable technique.For example, when they are formed of silicon oxide, they may be formedin a temperature range between about 50° C. and about 400° C., under apressure between about 1 Torr and about 10 Torr, using silane (SiH₄) andnitrous oxide (N₂O) as precursors. When they are formed of siliconnitride, they may be formed in a temperature range between about 250° C.and about 500° C., under a pressure between about 1 Torr and about 10Torr, using dichlorosilane (DCS) and ammonia (NH₃) as precursors. Whenthey are formed of silicon carbide, they may be formed in a temperaturerange between about 200° C. and about 450° C., under a pressure betweenabout 1 Torr and about 10 Torr, using precursors having trimethylsilylgroups. When they are formed of silicon oxynitride, they may be formedin a temperature range between about 200° C. and about 450° C., under apressure between about 1 Torr and about 10 Torr, using silane (SiH₄) andnitrous oxide (N₂O) as precursors. When they are formed of siliconoxy-carbide, they may be formed in a temperature range between about200° C. and about 450° C., under a pressure between about 1 Torr andabout 10 Torr, using Si-C containing gas reagents and oxygen containinggas reagents. When they are formed of silicon carbide nitride, they maybe formed in a temperature range between about 200° C. and about 450°C., under a pressure between about 1 Torr and about 10 Torr, using Si-Ccontaining gas reagents and nitrogen containing gas reagents. When theyare formed of silicon oxy-carbide nitride, they may be formed in atemperature range between about 200° C. and about 450° C., under apressure between about 1 Torr and about 10 Torr, using Si-C containinggas reagents and oxygen/nitrogen containing gas reagents. When they areformed of aluminum oxide/aluminum oxynitride/aluminum nitride, they maybe formed in a temperature range between about 200° C. and about 400°C., under a pressure between about 1 Torr and about 10 Torr, usingtrimethylamine (TMA) and water as precursors. When they are formed ofzirconium oxide/zirconium aluminum oxide/aluminum nitride, they may beformed in a temperature range between about 200° C. and about 400° C.,under a pressure between about 1 Torr and about 10 Torr, using zirconiumtetrachloride (ZrCl₄), trimethylamine (TMA) and water as precursors.When they are formed of amorphous silicon, they may be formed in atemperature range between about 350° C. and about 530° C., under apressure between about 0 Torr and about 1 Torr, using silane (SiH₄) anddisilane (Si₂H₆) as precursors. In some instances, the first spacer 310and the second spacer 312 may be formed to a thickness between about 0.5nm and about 15 nm.

A cross-section along the A-A′ plane may extend through multiple channelregions and source/drain regions where different types of gate routingand source/drain routing are adopted. Multiple regions and features thatmay not be shown along the same A-A′ plane are illustrated in FIG. 3 (aswell as in FIGS. 4-11 ) for illustration purposes and such illustrationdoes not limit the scope of the present disclosure unless otherwiseexpressly described. In embodiments represented in FIG. 3 (as well as inFIGS. 4-11 ), the cross-section goes through gate structure 320,source/drain contact structure (including, for example, the source/draincontact 332 and source/drain cap layer 334) 330, gate structure 320A,source/drain contact structure 330A, gate cut feature 320B andsource/drain contact isolation feature 330B. In some instances, gatestructure 320 and source/drain contact structure 330 may appear in thesame plane. In some other instances, gate structure 320A andsource/drain contact structure 330A may appear in the same plane. Instill other instances, gate cut feature 320B and source/drain contactisolation feature 330B may appear in the same plane. When the gatereplacement process is used, the gate cut feature 320B may be formed byfilling in a first fill material 317 in openings such that a metal layerlike metal layer 322 cannot be deposited in the openings. Similarly, thesource/drain contact isolation feature 330B may be formed by filling insecond fill material 319 in openings such that a source/drain contactlayer cannot be deposited in the openings. As shown in FIG. 3 , the gatecut feature 320B does not include any gate dielectric layer, metal layeror gate cap layer. Similarly, the source/drain contact isolation feature330B does not include any source/drain contact or source/drain caplayer. The gate cut feature 320B separate gate structures, such as thegate structure 320A. The source/drain contact isolation feature 330Bseparate source/drain contact structures, such as the source/draincontact structure 330A.

The method 200 then proceeds to block 204 where a gate contact via and asource/drain contact via are formed. For example, with reference toFIGS. 3 and 4 and in an embodiment of block 204, a gate contact via 326is formed through the first SAC dielectric layer 316 to electricallycouple to the gate cap layer 324 and a source/drain contact via 336 isformed through the second SAC dielectric layer 318 to electricallycouple to the source/drain cap layer 334 using suitable lithographytechniques. An example process may include forming a photoresist layer(resist) over the first SAC dielectric layer 316 and the second SACdielectric layer 318, exposing the resist to a pattern, performingpost-exposure bake processes, and developing the resist to form amasking element including the resist. With the masking element exposingregions where the via openings are to be formed, via openings may beetched through the first SAC dielectric layer 316 and the second SACdielectric layer 318. Then conductive material may be deposited in thevia openings and the masking element. Excess conductive material and aportion of the SAC layers are then removed by planarization processes,such as chemical mechanical polishing (CMP) to form a planar topsurface, as shown in FIG. 4 . The conductive material for the gatecontact via 326 and the source/drain contact via 336 may include W, TiN,TaN, WN, Re, Ir, Ru, Mo, Al, Cu, Co, Ni, or combinations thereof.

A cross-sectional view along a plane along line A-A′ may or may notextend through the gate contact via and the source/drain contact via atthe same time. For example, the cross-sectional plane of the device 300in FIG. 4 extend through the gate contact via 326 for the gate structure320 and the source/drain contact via 336 for the source/drain contactstructure 330 (including for example the source/drain contact 332 andthe source/drain cap layer 334). However, in this example, thecross-sectional plane may miss the gate contact via for the gatestructure 320A and the source/drain contact via for the source/draincontact structure 330A (including for example the source/drain contact332 and the source/drain cap layer 334).

Referring to FIG. 2 , after the gate contact via 326 and thesource/drain contact via 336 are formed, the method 200 proceeds toblock 206 where the second spacers 312 are removed to form air gaps1312, as illustrated in FIG. 4 and FIG. 5 . In some embodiments, thesecond spacers 312 (in FIG. 4 ), the first SAC dielectric layer 316, thesecond SAC dielectric layer 318, the first fill material 317, and thesecond fill material 319 are removed by etching while the first spacers310, the liner 314, the gate contact via 326, and the source/draincontact via 336 remain substantially unetched. The removal of the secondspacers 312 may be referred to as a spacer etch-back process. In someimplementations, the spacer etch-back process may be performed by dryetch, wet etch or a combination thereof by taking advantage of relativeetching selectivity among different materials. That is, the layers thatare to be removed at block 206, including the second spacers 312 (inFIG. 4 ), the first SAC dielectric layer 316, the second SAC dielectriclayer 318, the first fill material 317, and the second fill material319, may be formed with material that may be preferentially removedusing an etching chemistry that etches the first spacers 310, the liner314, the gate contact via 326, and the source/drain contact via 336 at aslower rate. For example, the second spacers 312 (in FIG. 4 ), the firstSAC dielectric layer 316, the second SAC dielectric layer 318, the firstfill material 317, and the second fill material 319 may be formed ofsilicon oxide and the first spacers 310 and the liner 314 may be formedof silicon nitride. In this example, the dry etchant or the wet etchantused in the spacer etch-back process may be one that is more selectiveto silicon oxide.

In some embodiments represented in FIG. 5 , opening 410, opening 420,opening 430, opening 440, opening 450, and opening 460 may be formedwithin the workpiece after block 206. Among them, the opening 410surrounds the gate contact via 326, the opening 420 surrounds thesource/drain contact via 336, the opening 430 is over the gate structure320A, the opening 440 is over the source/drain contact structure 330A,the opening 450 is over the gate cut feature 320B, and the opening 460is over the source/drain contact isolation feature 330B.

Reference is now made to FIG. 2 and FIG. 6 . The method 200 proceeds toblock 208 where a first sealing layer 500 is deposited over theworkpiece. In some embodiments, the process to deposit the first sealinglayer 500 is selected such that the first sealing layer 500 is conformalto the top surface of the workpiece of the device 300. In someimplementations, the process to deposit the first sealing layer 500 isisotropic such that the first sealing layer 500 would thicken near bothsides of the top opening of the air gaps 1312 (FIG. 5 ) and eventuallyplug the top opening of the air gap, leaving a plugged air gap 1312′. Insome instances, the process to deposit the first sealing layer 500 maybe anisotropic. As the width W of the air gap 1312 may be relativelysmall, such as between about 2 nm and about 4 nm, and the height of theair gap 1312 may be relatively large, such as between about 10 nm andabout 50 nm, the air gap 1312 may have an aspect ratio (height overwidth, H/W) about 3 or more. With such ranges of aspect ratio, ananisotropic process to deposit the first sealing layer 500 may plug thetop opening of the air gap 1312 without filling it. The first sealinglayer 500 may include a dielectric material such as silicon oxide,silicon nitride, silicon carbide, silicon oxynitride, siliconoxy-carbide, silicon carbide nitride, silicon oxy-carbide nitride,aluminum oxide, aluminum oxynitride, aluminum nitride, zirconium oxide,zirconium aluminum oxynitride, aluminum nitride, amorphous silicon, or acombination thereof. In some embodiments, the first sealing layer 500may be deposited using the temperature ranges, pressure ranges andprecursors described above with respect to the formation of the firstspacer 310, the second spacer 312, the liner 314, the first SACdielectric layer 316, the second SAC dielectric layer 318.

Referring now to FIG. 2 and FIG. 7 , the method 200 proceeds to block210 where a second sealing layer 600 is deposited over the first sealinglayer 500. In some embodiments, a process that has limited hole-fillingcapability may be intentionally selected to deposit the second sealinglayer 600. Example processes for the operation in block 210 may includeCVD or spin coating. As illustrated in FIG. 7 , because of the limitedhole-filling capability of the process, air pockets 610, 620, 630, and640 may be created at block 210. The second sealing layer 600 mayinclude a dielectric material such as silicon oxide, silicon nitride,silicon carbide, silicon oxynitride, silicon oxy-carbide, siliconcarbide nitride, silicon oxy-carbide nitride, aluminum oxide, aluminumoxynitride, aluminum nitride, zirconium oxide, zirconium aluminumoxynitride, aluminum nitride, amorphous silicon, or a combinationthereof. In some embodiments, the second sealing layer 600 may bedeposited using the temperature ranges, pressure ranges and precursorsdescribed above with respect to the formation of the first spacer 310,the second spacer 312, the liner 314, the first SAC dielectric layer316, the second SAC dielectric layer 318.

Referring now to FIG. 2 and FIG. 8 , the method 200 proceeds to block212 where a CMP process is performed on the workpiece. The CMP processplanarizes a top surface of the workpiece of device 300 such that topsurfaces of the first spacer 310, the liner 314, the gate contact via326, the source/drain contact via 336, the remaining portion of thesecond sealing layer 600 are coplanar. The remaining portion of thesecond sealing layer 600 define the air pockets 610, 620, 630, and 640.In some embodiments represented in FIG. 8 , after the CMP process, aplug feature 510, which is formed of the first sealing layer 500, may beformed between the first spacer 310 and the liner 314 to define an upperboundary of the plugged air gap 1312′.

In some alternative embodiments illustrated in FIG. 10 , the gatecontact via 326 and an alternative source/drain contact via 3361 may beformed separately. For example, the gate contact via 326 may be formedusing operations described with respect to blocks 210 and 212 and thealternative source/drain contact via 3361 may then be formed usingsimilar operations afterwards. For another example, the gate contact via326 may be formed after the alternative source/drain contact via 3361.In these alternative embodiments, the gate contact via 326 and thealternative source/drain contact via 3361 may not be coplanar and one ofthem may have a greater height relative to the substrate (FIG. 1 ) thanthe other.

Referring now to FIG. 2 , the method 200 proceeds to block 214 wherefurther processes are performed. For example, subsequent processing mayform various multilayers interconnect features (e.g., metal layers andinterlayer dielectric layers) on the substrate, configured to connectthe various features to form a functional circuit that may include oneor more FinFET devices. In furtherance of the example, a multilayerinterconnection may include vertical interconnects, such as vias orcontacts, and horizontal interconnects, such as metal lines. The variousinterconnection features may employ various conductive materialsincluding copper, tungsten, and/or silicide. In one example, a damasceneand/or dual damascene process is used to form a copper relatedmultilayer interconnection structure.

In some embodiments, the air pockets 610, 620, 630, and 640 may beclosed and completely surrounded by the second sealing layer 600, asillustrated in FIGS. 8 and 9 . In those embodiments, the air pockets610, 620, 630, and 640 are completely sealed by the second sealing layer600. In some alternative embodiments illustrated in FIGS. 10 and 11 ,the air pockets 610, 620, 630, and 640 may not be completely surroundedby the second sealing layer 600 and may be referred to as open airpockets 610′, 620′, 630′, and 640′. In these embodiments, the openingair pockets 610′, 620′, 630′, and 640′ are not completely sealed by thesecond sealing layer 600 and each includes an opening through topsurfaces of the gate structure 320A, source/drain contact structure330A, gate cut feature 320B, and source/drain contact feature isolation330B, respectively. It is noted that these open air pockets 610′, 620′,630′, and 640′, though not sealed by the second sealing layer 600, maybe sealed off by an ILD layer formed at block 214.

Thus, the various embodiments described herein offer several advantagesover the existing art. It will be understood that not all advantageshave been necessarily discussed herein, no particular advantage isrequired for all embodiments, and other embodiments may offer differentadvantages. For example, embodiments discussed herein include structuresand methods for providing an air gap that extend not only between a gatestructure and a source/drain contact, but also between a gate contactvia and a source/drain contact via. The presence of the air gap mayprovide a reduced spacer dielectric constant, resulting in reduction ofparasitic capacitance between a gate contact via and an adjacentsource/drain contact via and improved speed and performance of thesemiconductor device. In some embodiments, because the air gapsufficiently reduces the dielectric constant, the device 300 may beformed with a slot gate contact via 326′ that is coterminous with thegate cap layer 324 along the Y direction and a slot source/drain contactvia 336′ that is coterminous with the source/drain cap layer 334 alongthe Y direction, as illustrated in FIG. 9 . The wider slot gate contactvia 326′ and slot source/drain contact via 336′ in FIG. 9 may provideadditional benefits, such as further reducing the contact resistancebetween the gate cap layer 324 and the slot gate contact via 326′,between the slot gate contact via 326′ and overlying interconnectstructures, between the source/drain cap layer 334 and the slotsource/drain contact via 336,’ and between the slot source/drain contactvia 336′ and the overlying interconnect structures. Additionalembodiments and advantages will be evident to those skilled in the artin possession of this disclosure.

In some alternative embodiments illustrated in FIG. 11 , the slot gatecontact via 326′ and an alternative slot source/drain contact via 3361′may be formed separately. For example, the gate contact via 326′ may beformed and the alternative slot source/drain contact via 3361′ may thenbe formed using similar operations afterwards. For another example, theslot gate contact via 326′ may be formed after the alternative slotsource/drain contact via 3361′. In these alternative embodiments, theslot gate contact via 326′ and the alternative slot source/drain contactvia 3361′ may not be coplanar and one of them may have a greater heightrelative to the substrate (FIG. 1 ) than the other.

Thus, one of the embodiments of the present disclosure provides asemiconductor device. The semiconductor device includes a fin extendingfrom a substrate, a gate structure over a channel region of the fin, asource/drain contact over a source/drain region of the fin, a gate cutfeature adjacent the gate structure, a source/drain contact isolationfeature adjacent the source/drain contact, a spacer extending along asidewall of the gate cut feature and a sidewall of the gate structure, aliner extending along a sidewall of the source/drain contact isolationfeature and a sidewall of the source/drain contact; and an air gapsandwiched between the spacer and the liner. The gate cut feature andthe source/drain contact isolation feature are separated by the spacer,the air gap and the liner.

In some embodiment, the gate structure and the source/drain contact areseparated by the air gap. In some implementations, the semiconductordevice further includes a first dielectric layer over the gate structureand the source/drain contact, a gate contact via over and electricallycoupled to the gate structure, and a source/drain contact via over andelectrically coupled to the source/drain contact. The gate contact viaextends through the first dielectric layer over the gate structure. Thesource/drain contact via extends through the first dielectric layer overthe source/drain contact. The gate contact via and the source/draincontact via are further separated by a portion of the first dielectriclayer. In some instances, the semiconductor device further includes aplug feature over the air gap between the spacer and the liner. In someembodiments, the gate cut feature includes a first sealing layer, asecond sealing layer over the first sealing layer, and an air pocket inthe second sealing layer. In some implementations, the air pocket issurrounded by the second sealing layer.

In another of the embodiments, a semiconductor device of the presentdisclosure is provided. The semiconductor device includes asemiconductor feature having a channel region and a source/drain regionadjacent to the channel region, a gate structure over the channelregion, a gate contact via over and electrically coupled to the gatestructure, a source/drain contact over the source/drain region, asource/drain contact via over and electrically coupled to thesource/drain contact, and an air gap. The gate contact via and thesource/drain contact via are separated by the air gap.

In some embodiments, the semiconductor device further includes aplurality of spacers and a plurality of liners. The semiconductorfeature extends in a first direction. The gate structure is sandwichedbetween two of the plurality of spacers along the first direction. Thesource/drain contact is sandwiched between two of the plurality ofliners along the first direction. In some implementations, the air gapis sandwiched between one of the plurality of spacers and one ofplurality of the liners. In some instances, the gate contact via extendsbetween the two of the plurality of spacers and the source/drain contactvia extends between the two of the plurality of liners. In someembodiments, the gate contact via and the source/drain contact via areseparated by one of the plurality of spacers, one of the plurality ofliners, and the air gap. In some implementations, the gate structure andthe source/drain contact are separated by the air gap. In someembodiments, the semiconductor device further includes a plug featureover the air gap. In some implementations, the semiconductor devicefurther includes a first dielectric layer over the gate structure andthe source/drain contact. The gate contact via extends through the firstdielectric layer over the gate structure. The source/drain contact viaextends through the first dielectric layer over the source/draincontact. The gate contact via and the source/drain contact via arefurther separated by a portion of the first dielectric layer. In someinstances, the gate structure further includes a metal layer and a firstcap layer over the metal layer. The semiconductor device furtherincludes a second cap layer over the source/drain contact. A portion ofthe first cap layer is between the gate contact via and the metal layerand a portion of the second cap layer is between the source/draincontact via and the source/drain contact. In some examples, the firstcap layer and the second cap layer each includes tungsten, cobalt,nickel, ruthenium, titanium, titanium nitride, tantalum, or tantalumnitride.

In yet another of the embodiments, a method of forming a semiconductordevice is provided. The method includes receiving a workpiece thatincludes a substrate, a fin extending from the substrate, a gatestructure over a channel region of the fin, a plurality of first spacersand a plurality of second spacers, a source/drain contact over asource/drain region of the fin, a plurality of liners. The source/draincontact is sandwiched between two of the plurality of liners and thegate structure is sandwiched between two of the plurality of firstspacers. The two of the plurality of first spacers are sandwichedbetween two of the plurality of second spacers. The method furtherincludes forming a gate contact via over and electrically coupled to thegate structure, forming a source/drain contact via over the source/draincontact, and after the forming of the source/drain contact via,selectively removing the plurality of second spacers to form air gapsextending between the gate contact via and the source/drain contact via.

In some embodiments, the method further includes forming a first sealinglayer over the workpiece. In some implementations, the method furtherincludes forming a second sealing layer over the first sealing layer. Insome instances, the method further includes forming a first sealinglayer over the workpiece using a first deposition process and forming asecond sealing layer over the first sealing layer using a seconddeposition process. The first deposition process is different from thesecond deposition process.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A semiconductor device, comprising: a finextending from a substrate, the fin extending lengthwise along adirection and comprising a channel region and a source/drain regionadjacent to the channel region; a gate structure over the channelregion; a source/drain contact over the source/drain region; a gate cutfeature adjacent the gate structure; a source/drain contact isolationfeature adjacent the source/drain contact; a spacer extending along asidewall of the gate cut feature and a sidewall of the gate structure; aliner extending along a sidewall of the source/drain contact isolationfeature and a sidewall of the source/drain contact; and an air gapsandwiched between the spacer and the liner, wherein the gate cutfeature and the source/drain contact isolation feature are separated bythe spacer, the air gap and the liner.
 2. The semiconductor device ofclaim 1, wherein the gate structure and the source/drain contact areseparated by the air gap along the direction.
 3. The semiconductordevice of claim 1, further comprising: a gate cap layer disposed on thegate structure; and a source/drain cap layer disposed on thesource/drain contact, wherein the spacer also extends along a sidewallof the gate cap layer, wherein the liner also extends along a sidewallof the source/drain cap layer.
 4. The semiconductor device of claim 3,wherein the gate cap layer and the source/drain cap layer comprise W,Co, Ni, Ru, Ti, Ta, TiN, or TaN.
 5. The semiconductor device of claim 3,further comprising: a first dielectric layer over the gate cap layer;and a second dielectric layer over the source/drain cap layer, whereinthe spacer also extends along a sidewall of the first dielectric layer,wherein the liner also extends along a sidewall of the second dielectriclayer.
 6. The semiconductor device of claim 5, further comprising: agate contact via extending through the first dielectric layer toelectrically coupled to the gate cap layer; and a source/drain contactvia extending through the second dielectric layer to electrically coupleto the source/drain contact, wherein, along the direction, the gatecontact via is spaced apart from the spacer by a portion of the firstdielectric layer, wherein, along the direction, the source/drain contactvia is spaced apart from the liner by a portion of the second dielectriclayer.
 7. The semiconductor device of claim 6, wherein, along thedirection, the gate contact via is spaced apart from the source/draincontact via by the spacer, the liner, and the air gap.
 8. Thesemiconductor device of claim 1, further comprising a plug feature overthe air gap between the spacer and the liner.
 9. The semiconductordevice of claim 1, wherein top surfaces of the gate cut feature, thesource/drain contact isolation feature, the liner, and the spacer arecoplanar.
 10. A semiconductor structure, comprising: an active regionextending lengthwise along a first direction and comprising a channelregion and a source/drain region adjacent to the channel region; a gatestructure over the channel region; a source/drain contact over thesource/drain region; a gate cut feature adjacent the gate structurealong a second direction perpendicular to the first direction; asource/drain contact isolation feature adjacent the source/drain contactalong a second direction perpendicular to the first direction; a firstsealing feature over the gate structure; a second sealing feature overthe source/drain contact; a spacer extending along a sidewall of thegate cut feature, a sidewall of the first sealing feature and a sidewallof the gate structure; a liner extending along a sidewall of thesource/drain contact isolation feature, a sidewall of the second sealingfeature and a sidewall of the source/drain contact; and an air gapsandwiched between the spacer and the liner.
 11. The semiconductorstructure of claim 10, wherein the gate cut feature and the source/draincontact isolation feature are separated by the spacer, the air gap andthe liner.
 12. The semiconductor structure of claim 10, wherein the gatecut feature comprises a first inner layer and a first outer layer,wherein a composition of the first outer layer is the same as acomposition of the first sealing feature, wherein the first inner layeris spaced apart from the spacer by the first outer layer.
 13. Thesemiconductor structure of claim 12, wherein the gate cut featurecomprises a first air pocket trapped in the first inner layer.
 14. Thesemiconductor structure of claim 10, wherein the source/drain contactisolation feature comprises a second inner layer and a second outerlayer, wherein a composition of the second outer layer is the same as acomposition of the second sealing feature, wherein the second innerlayer is spaced apart from the liner by the second outer layer.
 15. Thesemiconductor structure of claim 14, wherein the source/drain contactisolation feature comprises a second air pocket trapped in the secondinner layer.
 16. The semiconductor structure of claim 10, furthercomprising: a gate cap layer sandwiched directly between the gatestructure and the first sealing feature; and a source/drain cap layersandwiched directly between the source/drain contact and the secondsealing feature.
 17. A method of forming a semiconductor device,comprising: receiving a workpiece comprising: a substrate, a finextending from the substrate, the fin comprising a channel region and asource/drain region adjacent to the channel region, a gate structureover the channel region, a plurality of first spacers and a plurality ofsecond spacers, wherein the gate structure is sandwiched between two ofthe plurality of first spacers, the two of the plurality of firstspacers are sandwiched between two of the plurality of second spacers, asource/drain contact over the source/drain region, a plurality ofliners, wherein the source/drain contact is sandwiched between two ofthe plurality of liners; forming a gate contact via over andelectrically coupled to the gate structure; forming a source/draincontact via over the source/drain contact; and after the forming of thesource/drain contact via, selectively removing the plurality of secondspacers to form air gaps extending between the gate contact via and thesource/drain contact via.
 18. The method of claim 17, further comprisingforming a first sealing layer over the workpiece.
 19. The method ofclaim 18, further comprising forming a second sealing layer over thefirst sealing layer.
 20. The method of claim 19, furthering comprisingforming a first sealing layer over the workpiece using a firstdeposition process and forming a second sealing layer over the firstsealing layer using a second deposition process, wherein the firstdeposition process is different from the second deposition process.